• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An error correcting encoding and decoding system for transmission and reception of digital data is arranged for high error-correcting ability of both burst errors and random errors. In encoding apparatus a digital signal is processed as a plurality of word sequences. The words are interleaved into a different arranging order and are subjected to different relative amounts of delay. Then, first check words are generated to satisfy a parity detection matrix, such as a Reed-Solomon code matrix. After this, the resulting data words and first check words are again interleaved and are provided with respective different amounts of delay. Then, second check words are generated to satisfy a similar matrix. Finally, the first and second check words and the data words are interleaved prior to transmission. In complementary decoding apparatus, the cross-interleaved received signal is de-interleaved in a fashion complementary to the interleaving performed during transmission and the data words are delayed a complementary amount. The received data words are decoded by providing syndromes generated according to the parity detection matrix and burst or random errors are corrected by the check words.
    公开号:SU1271382A3
    申请号:SU813288050
    申请日:1981-05-20
    公开日:1986-11-15
    发明作者:Одака Кентаро；Сако Йоихиро；Ивамото Икуо；Дои Тошитада；Баренд Фриес Лодевийк
    申请人:Н.В.Филипс Глоэлампенфабрикен (Фирма)；
    IPC主号:
    专利说明:

     O1
    f
    The invention is intended to increase the reliability of information transmission in digital multichannel systems and can be applied to high-quality recording and sound reproduction devices.
     The aim of the invention is to increase the reliability of the transmission of information.
    A block of skem is shown on the screen: a coder with error correction; on . FIG. 2 alignment of signals during transmission; in fig. 3 is a block diagram of an apparatus for decoding data words (an example of an error correction decoder); in fig. 4 and 5 diagrams of device operation when decoding data words with error correction; in fig. 6 is a block diagram of a second encoder; in fig. 7 is a block diagram of devices for decoding data words with error correction, option; FIG. 8 is a block diagram of a third encoder; FIG. in fig. 9 - the same; on. 10 - block circuit of the fourth encoder; in fig. N the same.
    The encoder (Fig. 1) contains the block 1 of the first delay elements 2 2. 3 Rear, 4 ,, 4, 5 ,, 5 ,, 6, 6, 7 and 7, the first decoder 8 word-correction block 9 of the second delay elements, the decoder 10 word-correction, block 11 of third delay elements, inverters 12-15, a device for decoding data words contains (fig. 3) block 16 delay elements, inverters 17-20, word-correction decoder 21, block 22 of the second delay elements, second decoder 23 word by word correction, block 24 of the third delay elements. The second encoder (FIG. B) contains a signal interleaver 25, an encoder 26, a delay block 27, a correction block 28, a delay block 29. The device of FIG. 7 contains the multiplexer 30, the inverters 31., the high register 32, the block of delay elements 33, the A1 analog converter 34 and the multiplexer 35.
    g
    The device works as follows.
    In the decoding mode, the synchronization header is separated from the beginning. The remaining 32 codewords of each transmitting unit are fed to the input of the word-correction decoder 21. In the process of reproducing information possible
    3822
    mistakes. If there are no errors, then the 32 words that came to the input of the decoder are identical to the 32 words received from the output of the encoder with error correction. At the decoder, a de-interleaving process occurs, complementing the interleaving process in the encoder to return to the original order of information signals, after which errors are corrected. In block 16 (FIG. 3), the delay elements have a delay time equal to the transmission time of one word. Inverters 17–20 are provided for a sequence of second control words. At the output of the decoder 21, sets of symptoms S.,, S, and 5 are formed (Fig. 4), error correction is performed on the basis of these sets of symptoms.
    FIG. 4 shows the o-element GP (2), which is the root of the original and irreducible polynomial of degree M, F (X) X + x + x - + x + 1, From de; encoder 21 receives 24 KIM information sequences and 4 sequences of control words. An error pointer is added to each word of the information sequence, the bits of which are transmitted according to the scheme in the same way as information bits or control words,
    From the output of the decoder 21, the information sequence is fed to the second delay elements 22, which compensate for the delay introduced by the corresponding elements 9 (Fig. 1). From the output of the delay elements 22, signals arrive at the second decoder 23, in which from the parity detection matrix H (, 2 and input 28 words (l) generate a set of symptoms of Sji,
    S2i, Sz., (Fig, 5). r
    Based on a set of symptoms, error correction is then carried out. In the decoder 23, the pointer relating to the signal is erased, in which the error is corrected, while the pointer relating to the word in which it is impossible to eliminate the error remains. From the output of the decoder 23, a sequence of signals is supplied to the third delay elements 24, in which the sequences of words of even and odd orders are located in the initial state,
    In the device (Fig. 3), error correction is based on the use of the first control words P ,,,, PijniPi jnt- and Pijn,, and the correction of the error oc 1c:; annna on the use of the x control word / Q121) 0i2ni% pg wire mc one time. If the mentioned error corrections are performed more than twice, the ability to correct is increased and a smaller number of them remain uncorrected. The error correction code allows, for example, to correct up to two dictionary errors without using an indicator marking the position of errors and the error packet. corrected by cross-interlacing. Thus, effective correction of both random errors and error packets can occur. With an increase in the number of corrected words, the decoding algorithm becomes more complicated, but to correct only one dictionary error, using a simple encoder is sufficient. I find a device for decoding data words transmitted over a data transmission channel and block-protected by means of a correction code containing the first word-correction decoder, the first inputs of which are connected to the even, but two last, outputs of the transmission channel , characterized in that, in order to increase the reliability of information transfer, the first, second and third delay elements, inverters and the second word-correction decoder are odd in addition to the last two, the output is added to the device The transmission channel is connected to the second inputs of the first decoder through corrections through the first delay elements, the delay time of which corresponds to one pulse delay interval between even and odd transmission channels, the even second last and last transmission channels are connected to the third the inputs of the first word-correction decoder through series-connected inverters and the first delay elements, the odd penultimate and last outputs of the transmission channels are connected via inverters to the fourth inputs of the first word word decoder, the outputs of which are connected to the corresponding inputs of the second delay elements, each subsequent element of which has a delay time greater than the previous one by the delay of data words, the outputs of the second delay elements are connected to the corresponding inputs of the second word-correction decoder, the outputs of which through the corresponding third elements delays having a delay time equal to an integer number of pulse delay intervals between even and odd transmission channels are connected to you one register. i 2, A device for decoding data words transmitted over a data transmission channel and block-protected by means of a correction code containing the first word-correction decoder, the first inputs of which are connected to the even, but two last, outputs of the transmission channel, differing from the fact that , in order to increase the reliability of information transfer, in the device one input of the device’s serial signals through the demultiplexer directly, others through the corresponding inverters connected to the inputs of the output register Pa, whose outputs are connected via series-connected multiplexer and digital-to-analogue transducer to audio outputs of the device.
    -
    IL
    z
    -c
    权利要求:
    Claims (2)
    [1]
    Claim
    1. A device for decoding data words transmitted over a data channel 30 and block protected by means of a correction code, comprising a first word correction decoder, the first inputs of which are connected to even, except the last 35, outputs of the transmission channel, characterized in that, for the purpose of improve reliability of data transmission, the apparatus additionally introduced first, second and third delay elements 40, inverters and a second decoder Literal correction odd, but the last two channel outputs transmission unified with the second inputs of the first decoder 43 poslov- hydrochloric correction through the first delay elements, the delay time which co- f
    382 4 corresponds to one interval of the pulse delay between the even and odd transmission channels, the even penultimate and last transmission channels are connected to the third inputs of the first word-correction decoder through series-connected inverters and the first delay elements, the odd penultimate and last outputs of the transmission channels are connected to the fourth inputs through inverters the first word correction decoder, the outputs of which are connected to the corresponding inputs of the second delay elements, each subsequent element of which has a delay time longer than the previous one by a data word delay interval, the outputs of the second delay elements are connected to the corresponding inputs of the second word correction decoder, the outputs of which through the corresponding third delay elements having a delay time equal to an integer number of pulse delay intervals between even and odd transmission channels, connected to the output register.
    I
    [2]
    2. A device for decoding data words transmitted over a data channel and block protected by means of a correction code, comprising a first word correction decoder, the first inputs of which are connected to even, except the last two, outputs of the transmission channel, which means that, with In order to increase the reliability of information transfer, in the device some inputs of serial signals of the device through the demultiplexer directly, while others - through the corresponding inverters are connected to the inputs of the output register, outputs of koto-. Through a series-connected multiplexer and a digital-to-analog converter, they are connected to the sound outputs of the device.
    Riga 1 / IJ / 'Γ: S3C 3t la </ 5sl X — _ί __— r
    D »A_ = £
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    同族专利:
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    BR8103074A|1982-08-24|
    US4413340A|1983-11-01|
    BE888891A|1981-11-20|
    JPH0376051B2|1991-12-04|
    CA1163341A|1984-03-06|
    KR850001023B1|1985-07-18|
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    IN154622B|1984-11-17|
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    JP55067608A|JPH0376051B2|1980-05-21|1980-05-21|
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